CMOS is Complementary metal–oxide–semiconductor.
A thin layer of silicon dioxide (SiO2) of thickness tox (typically 2-50nm) which is an excellent insulator is grown on the surface substrate, covering the area between source and drain.
Next metal is deposited to form a 4 terminal device: Terminals are labeled Source (S), Gate(G), Drain (D) and Body (B).
This configuration forms 2 back to back diodes. With no bias voltage applied to the gate, the back to back diodes prevent current conduction from drain to source when a voltage VDS is applied.
Positive voltage applied at vGS causes the free holes (positive charge) to be repelled from the region of the substrate under the gate.
These holes are push downward into the substrate, creating a carrier depletion region (depletion region is populated by negative charge due to the neutralizing holes that have been pushed down).
In addition, the positive gate voltage attracts electrons from the n+ wells, creating an n region (channel) connecting the source and drain. Thus current can flow through this induced region. The MOSFET of figure 4.2 is referred to as a n-channel MOSFET (Note ann-channel MOSFET is formed in a p-type substrate. The value of vGS at which a sufficient number of mobile electrons accumulate in the channel region to form a conducting channel is called the threshold voltage and is denoted as (Vt). Vt ranges between 0.5 to 1.0V.
Having induced a channel and applying a positive voltage vDS, between the drain and source causes a current iD to flow through the induced channel.
VT – The threshold voltage
Operation Modes:
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1. Cut-off or sub-threshold mode
When VGS < VT
In this mode the device is turned off, and there is no conduction between drain and source. The current between drain and source should ideally be zero since the switch is turned off, there is a weak-inversion current, or subthreshold leakage. With MOSFET scaling subthreshold leakage composes a large percentage of total power consumption.
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