CMOS RF Noise Model

The dominant noise contributors in short-channel CMOS devices at radio frequencies are: 
 1. Channel thermal noise
The Channel thermal noise of mosfet is described by:
(in)^2=4kTγgdo
For long channel devices, the excess noise factor (γ) is 2/3. However, for short channel devices this factor can be higher.
2. Induced gate noise 
3. Parasitic gate and bulk resistance – those resistance are due to finite sheet resistance of the semiconductor materials can add to the overall noise floor of the MOSFET at high frequencies and if overlooked can easily become the dominant noise contributor for the device. It can be minimized by scaling the aspect ratio, adding fingers to the gate, and by contacting both ends of each finger of the transistor.    

  

CMOS Noise

Noise – small flactuation of the signal. will occur due to the random motion of the electrons.

Noise types:
1. CMOS Shot Noise
2. CMOS Thermal Noise
3. CMOS Flicker Noise
4. Noise power spectral density

Noise power spectral density

Noise Power Spectral Density describes the noise spectral content in a 1Hz bandwidth, or simply the spectrum of the noise.
The noise power spectral density describes how the power of a noise is distributed with frequency. 
The instantaneous power is then given by: P=S(t)^2

Using Wiener–Khinchin theorem, the PSD is the Fourier transform of the autocorrelation function, R(τ), of the signal: S(f) = ∫R(τ)e^(-2Ωifτ)dτ

CMOS Flicker Noise

CMOS Flicker Noise or 1/f noise is current noise

 MOSFETs have a higher f_c than JFETs or bipolar transistors which is usually below 2 kHz for the latter

i^2 = Kf*()

CMOS Thermal Noise

CMOS Thermal Noise is a voltage noise cause by the random thermal motion of the electron.

The thermal noise is independent of the DC current of the device.

v^2 = 4*K*T*R*df

K – Boltzman constant
R – the resistance of the device
T – temerature
df – bandwidth

CMOS Shot Noise

Shot Noise is a current noise. It is associated with the dc current flow across the pn junction.

(i)^2 = 2*q*Id*df [Ampers^2]

LMX2306 – 550 MHz PLL

LMX2306 – 550 MHz PLLatinum Low Power Frequency Synthesizer for RF Personal Communications

LMX2306/LMX2316/LMX2326
PLLatinum Low Power Frequency Synthesizer for RF
Personal Communications
LMX2306 550 MHz
LMX2316 1.2 GHz
LMX2326 2.8 GHz
General Description
The LMX2306/16/26 are monolithic, integrated frequency synthesizers with prescalers that are designed to be used to generate a very stable low noise signal for controlling the local oscillator of an RF transceiver. They are fabricated using National’s ABiC V silicon BiCMOS 0.5μ process. The LMX2306 contains a 8/9 dual modulus prescaler while the LMX2316 and the LMX2326 have a 32/33 dual modulus prescaler. The LMX2306/16/26 employ a digital phase locked loop technique. When combined with a high quality reference oscillator and loop filter, the LMX2306/16/26 provide the feedback tuning voltage for a voltage controlled oscillator to generate a low phase noise local oscillator signal. Serial data is transferred into the LMX2306/16/26 via a three wire interface (Data, Enable, Clock). Supply voltage can range from 2.3V to 5.5V. The LMX2306/16/26 feature ultra low current consumption; LMX2306 – 1.7 mA at 3V, LMX2316 – 2.5 mA at 3V, and LMX2326 – 4.0 mA at 3V. The LMX2306/16/26 synthesizers are available in a 16-pin TSSOP surface mount plastic package.
Features
* 2.3V to 5.5V operation
* Ultra low current consumption
* 2.5V VCC JEDEC standard compatible
* Programmable or logical power down mode:
— ICC = 1 μA typical at 3V
* Dual modulus prescaler:
— LMX2306 8/9
— LMX2316/26 32/33
* Selectable charge pump TRI-STATE® mode
* Selectable FastLock™ mode with timeout counter
* MICROWIRE™ Interface
* Digital Lock Detect
Applications
* Portable wireless communications (PCS/PCN, cordless)
* Wireless Local Area Networks (WLANs)
* Cable TV tuners (CATV)
* Pagers
* Other wireless communication systems  

CMOS

CMOS is Complementary metal–oxide–semiconductor.
A thin layer of silicon dioxide (SiO2) of thickness tox (typically 2-50nm) which is an excellent insulator is grown on the surface substrate, covering the area between source and drain.
Next metal is deposited to form a 4 terminal device: Terminals are labeled Source (S), Gate(G), Drain (D) and Body (B).
This configuration forms 2 back to back diodes. With no bias voltage applied to the gate, the back to back diodes prevent current conduction from drain to source when a voltage VDS is applied.
Positive voltage applied at vGS causes the free holes (positive charge) to be repelled from the region of the substrate under the gate.
These holes are push downward into the substrate, creating a carrier depletion region (depletion region is populated by negative charge due to the neutralizing holes that have been pushed down).
In addition, the positive gate voltage attracts electrons from the n+ wells, creating an n region (channel) connecting the source and drain. Thus current can flow through this induced region. The MOSFET of figure 4.2 is referred to as a n-channel MOSFET (Note ann-channel MOSFET is formed in a p-type substrate. The value of vGS at which a sufficient number of mobile electrons accumulate in the channel region to form a conducting channel is called the threshold voltage and is denoted as (Vt). Vt ranges between 0.5 to 1.0V.
Having induced a channel and applying a positive voltage vDS, between the drain and source causes a current iD to flow through the induced channel.

V_T – The threshold voltage

Operation Modes:

null

1. Cut-off or sub-threshold mode

When V_GS < V_T

In this mode the device is turned off, and there is no conduction between drain and source. The current between drain and source should ideally be zero since the switch is turned off, there is a weak-inversion current, or subthreshold leakage. With MOSFET scaling subthreshold leakage composes a large percentage of total power consumption.